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Core8051
Table 8 ? Special Function Register Reset Values (Continued)
dph1
pcon
tcon
tmod
tl0
tl1
th0
th1
ckcon
p1
dps
scon
sbuf
p2
ien0
ien1
p3
ip0
ip1
psw
85h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
90h
92h
98h
99h
A0h
A8h
B8h
B0h
A9h
B9h
D0h
00h
00h
00h
00h
00h
00h
00h
00h
01h
FFh
00h
00h
00h
FFh
00h
00h
FFh
00h
00h
00h
Dual Data Pointer High 1
Power Control
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
Timer 1, high byte
Timer 0, low byte
Timer 1, high byte
Clock Control (Stretch=1)
Port 1
Data Pointer Select Register
Serial Port 0, Control Register
Serial Port 0, Data Buffer
Port 2
Interrupt Enable Register 0
Interrupt Enable Register 1
Port 3
Interrupt Enable Register 0
Interrupt Enable Register 1
Program Status Word
External Special Function Registers
The external SFR interface services up to 101 off-core
special function registers. The off-core peripherals can
use all addresses from the SFR address space range 80H
to FFH except for those that are already implemented
inside the core.
Instruction Set
When a read instruction occurs with a SFR address that
has been implemented both inside and outside the core,
the read will return the contents of the internal SFR.
When a write instruction occurs with a SFR that has been
implemented both inside and outside the core, the value
of the external SFR is overwritten.
All Core8051 instructions are binary code compatible and
functional groups. In
Table 16 on page 16 , the
perform the same functions as they do with the industry
standard 8051. Table 9 on page 12 and Table 10 on
page 12 contain notes for mnemonics used in the various
Instruction Set tables. In Table 11 on page 12 through
Table 15 on page 15 , the instructions are ordered in
v6.0
instructions are ordered in the hexadecimal order of the
operation code. For more detailed information about
the Core8051 instruction set, refer to the Core8051
Instruction Set Details User’s Guide .
11
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